1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more particularly, to a semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line.
2. Description of the Background Art
As integration density of a logic integrated circuit is increased, the extension of developing period and the increase in developing cost have conventionally become problems. In order to solve such problems, a gate array has been recently employed to form a desired logic circuit as an LSI (Large-Scale Integrated Circuit). The gate array is manufactured by a manufacturing method of a master slice type comprising the preceding process referred to as a master process and the succeeding process referred to as a slice process. Elements such as a transistor, a diode and a register which are common to many kinds of semiconductor device are first formed in a chip in the master process and subsequently, interconnections for a signal and a power supply which are peculiar to the selected kinds of semiconductor device are provided in the slice process.
Thus, an LSI chip manufactured according to the usage comprises an internal logic gate region, an interconnection region and an input/output buffer region. The internal logic gate region is a region in which gates (basic cells) are regularly arranged, an interconnection region is a region for connecting the gates to each other, and the input/output buffer region is a region in which there are disposed input/output buffer cells each functioning as an interface between a logic circuit achieved in the internal logic gate region and another element outside of the LSI.
In the input/output buffer region, a transistor having larger driving ability than that of a transistor used in the internal logic gate region is formed in order to drive another element outside of the LSI. In addition, since the input/output buffer region must function as an interface as described above, it must receive a signal at a TTL (Transistor-Transistor Logic) level or a CMOS (Complimentary Metal Oxide Semiconductor) level. Thus, in the input/output buffer region, a transistor of special size is formed.
FIG. 1 is a diagram showing a structure of a complimentary MOS semiconductor integrated circuit device constituting a conventional gate array. In FIG. 1, bonding pads 2 are disposed in the periphery of a semiconductor chip 1, and an internal logic gate portion 3 is disposed in the central portion of the semiconductor chip 1. The internal logic gate portion 3 is structured by regularly arranging basic cells each comprising a pair of a P-type MOS transistor and an N-type MOS transistor in an array manner. Input/output buffers 4 are provided between the bonding pads 2 and the internal logic gate portion 3 in such a manner as to surround the internal logic gate portion 3 in order to provide an interface between the internal logic gate portion 3 and the outside of the chip.
FIG. 2 is a diagram showing a detailed structure of each of the input/output buffers 4 and the peripheral portions. In FIG. 2, the input/output buffer 4 is divided into input/output buffer cells 5 the number of which is the same as that of the bonding pads 2, the bonding pads 2 and the input/output buffer cells 5 being in one-to-one correspondence to each other. Each of this input/output buffer cells 5 comprises a P-type MOS transistor region for output (referred to as output P-MOS portion hereinafter) 6, an N-type MOS transistor region for output (referred to as output N-MOS portion hereinafter) 7, a P-type MOS transistor region for input and logic (referred to as input/logic P-MOS portion hereinafter) 8 and an N-type MOS transistor region for input and logic (referred to as input/logic N-MOS portion hereinafter) 9 respectively having inherent sizes corresponding to the driving ability or the like as described above.
P-type region PA and an N-type region NA are disposed in this order in the direction from the bonding pads 2 to the internal logic gate portion 3 (referred to as cell disposing direction hereinafter). In the P-type region PA, the output P-MOS portion 6 and the input/logic P-MOS portion 8 are arranged in the direction in which the bonding pads 2 are arranged (referred to as pad arranging direction hereinafter). On the other hand, in the N-type region NA, the output N-MOS portion 7 and the input/logic N-MOS portion 9 are respectively arranged corresponding to the output P-MOS portion 6 and the input/logic P-MOS portion 8. Until the master process, this input/output buffer cell 5 is structured to be able to select any one of respective roles of an input buffer, an output buffer, a tri-state output buffer and an input/output bidirectional buffer.
First, if and when the input/output buffer cell is used as the input buffer, the input/logic P-MOS portion 8 and the input/logic N-MOS portion 9 are connected to each other, and the other portions 6 and 7 are not used. Then, when the input/output buffer cell 5 is used as the output buffer, the output P-MOS portion 6 and the output N-MOS portion 7 are connected to each other, and the other portions 8 and 9 are not used. When the input/output buffer cell 5 is used as the tri-state output buffer and the input/output bidirectional buffer, respectively, the output P-MOS portion 6 is connected to the output N-MOS portion 7, as well as to the input/logic P-MOS portion 8, and the input/logic N-MOS portion 9 is connected to the output N-MOS portion 7, as well as to the input/logic P-MOS portion 8. Therefore, considering the connecting relation between the regions, the disposition as shown in FIG. 2 is achieved in the input/output buffer cell 5.
The conventional input/output buffer cell 5 is arranged as shown in FIG. 2, so that the size La of the input/output buffer cell 5 in the pad arranging direction is larger than the size Lb of the bonding pad 2 in the pad arranging direction. In addition, in the conventional semiconductor integrated circuit device, one input/output buffer cell 5 is provided corresponding to one bonding pad 2. From the foregoing, the maximum number of input pins which can be provided on one semiconductor chip is determined depending on the size of the input/output buffer cell 5 in the pad arranging direction.
Meanwhile, as miniaturizing techniques progress, integration of internal logic gates has been recently improved. Correspondingly, the number of input/output pins must be increased. However, since the conventional semiconductor integrated circuit device is structured as described above, the number of input/output buffer cells 5 must be increased by the same number in order to increase the number of the input/output pins, from the above described reasons. Thus, considering the size of the conventional input/output buffer cell 5 in the pad arranging direction, the number of the input/output buffer cells 5 which can be disposed on one semiconductor chip 1 has a limit. In addition, if the number of the input/output buffer cells 5 is increased beyond the limit, the chip size of the semiconductor chip 1 is significantly increased.
Additionally, since transistors for output in the conventional input/output buffer cell 5 are respectively formed in fixed sizes, only a limited given constant driving ability can be obtained. If a combination of basic cells in the internal logic gate portion is changed, the sizes of the transistors in the input/output buffer cell 5 must be correspondingly changed to provide sufficient driving capacity.
Additionally, since transistors for input in the conventional input/output buffer cell 5 are respectively formed in fixed sizes, only an interface at a constant level can be obtained.